The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
During the scaling trend, various materials have been implemented for the gate electrode and gate dielectric for CMOS devices. Metal-oxide semiconductor (MOS) transistors have typically been formed with polysilicon gate electrodes. Polysilicon material has been used due to its thermal resistive properties during high temperature processing, which allows it to be annealed at high temperatures along with source/drain structures. Furthermore, polysilicon's ability to block the ion implantation of doping atoms into the channel region is advantageous, as it allows for the easy formation of self aligned source/drain structures after gate patterning.
However, there has been a desire to fabricate these devices with a metal material for the gate electrode and a high-K dielectric for the gate dielectric. It may be advantageous to replace the polysilicon gate electrode with a metal gate electrode to improve device performance as feature sizes continue to decrease. One process of forming a metal gate stack is termed a “gate last” process in which the final gate stack is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that are be performed after formation of the gate. In the gate last process, a dummy poly gate is initially formed and may continue with processing until deposition of an interlayer dielectric (ILD). A chemical mechanical polishing (CMP) is typically performed on the ILD layer to expose the dummy poly gate. The dummy poly gate may then be removed and replaced with a true metal gate. As device sizes continue to get scaled down, it may be harder to control the thickness of the metal material deposited over the gate electrode. A bottom coverage effect may lead to uneven thickness for these metal materials depending on the size of the gate which can adversely affect subsequent processing. In addition, photoresist peeling may be an issue, especially if the etching time is long.